Letter to santa writing paper

Saturday, June 27, 2020

How to Write Essays With Proper Essay Topics

<h1>How to Write Essays With Proper Essay Topics</h1>Hard work exposition points ought to be pondered before you start composing. The motivation behind a paper is to convey your contemplations, emotions and perspectives on the issue being referred to. Along these lines, the subject of your article will be the beginning stage for your exposition and you should ensure that you are making it as intriguing as could reasonably be expected. The point must be elegantly composed so that it becomes eye getting and peruser intrigue grows.You should likewise ensure that you utilize a pen or scratch pad to write down your framework paper themes. Before you start composing, you should initially have a thought of the organization you need to go with. On the off chance that you will compose a scientific exposition, at that point you can select a sequential flow.Once you have made up your blueprint for t he article subjects, you should record all the theme in a sensible request. In spite of the fact that you may have your specific point at the top of the priority list, it is smarter to compose the article theme before you begin writing to keep away from any issues later. After you have recorded the thought, ensure that you have dense the subtleties in an unmistakable manner.If you need to make effect and dazzle your perusers, at that point you should begin placing the diagram into a layout. As such, it will turn out to be simple for you to separate the article subjects into sentences and configuration them in the best possible manner.You can either utilize the diagram as your reason for your papers or you can utilize the blueprint as a guide while composing your own papers. It can likewise assist you with choosing which theme to compose and how to begin your essays.Befor e you start composing, it is significant that you ensure that you have made a framework for the article subjects. When you have chosen the subject of your article, you should then concentrate on the point and compose from that viewpoint.The thought is to take the peruser on an excursion as you compose, so you should focus on the topic of the exposition and not the style of composing. So on the off chance that you can viably concentrate on your subject, at that point it will make your composing intriguing and keeps the peruser hooked.

Wednesday, June 17, 2020

Writing Book Name in Essay Format

<h1>Writing Book Name in Essay Format</h1>If you will compose a book name in paper design, you should design it out for some time first. Here are a few hints that will assist you with this, and assist you with abstaining from submitting botches when you're composing. There are no correct strategies, however there are a few thoughts that you can use to make a book name in paper format.The initial step is to decide the title of your book. The title will be the absolute first thing you have composed when you go to get an exposition from a school or school. At the end of the day, you should attempt to make the title coordinate your subject and intrigue. Don't simply utilize the book name itself as your title, be that as it may. Utilize the title for a couple of sentences, or for the principal passage in your essay.After you decide the title, you'll have to expound on the book itself. What's y our proposition, and how can it identify with the book? Consider the best components of the book and check whether any of them will fit into your exposition. A portion of these would incorporate the primary character's demeanor, how the storyline constructs, the general plot, the activity, the initial hardly any sections, etc. Keep in mind, your title will do a great deal of the talking here, so go through your creative mind to accompany a reasonable theme.The subsequent stage is to make the paper. Your exposition ought to have all the angles you've examined in the title of your book, in addition to some that you haven't. You should ensure your title and article are associated some way or another, since they're comparative enough to help interface them. A smart thought is start your exposition with a couple of sentences about your book title, and end it with the title itself.Once you have the paper, you'll n eed to compose your article. Your paper ought to have a similar tone as your title. You should utilize a similar sentence structure and utilize comparable language all through. This additionally applies to your paper title. Utilize a similar sentence structure, and your title ought to do the equivalent job.You have a couple of alternatives with regards to the organization of your book name in paper position. You can utilize some different structures like the APA position or the MLA design, which are both mainstream, and a mix of both formats.Writing book name in article configuration can take some work, yet it tends to be fun also. It's single direction to test your abilities recorded as a hard copy by expounding on a book title. It's likewise an incredible method to evaluate different distinctive exposition topics.

Thursday, June 4, 2020

How to Write a 6 Page College Essay Samples

<h1>How to Write a 6 Page College Essay Samples</h1>There are numerous subjects on which to rehearse your composing abilities, for example, how to compose a 6-page school paper tests. Composing test papers requires the master pen and creative mind of a craftsman to make it worth perusing. Composing test expositions will likewise make you mindful of the deficiencies of your normal essays.To start with, there is something in particular about composing test papers that don't show up in their normal assignments. While you may have a feeling on an article subject, the paper despite everything can't be viewed as a solid exposition without having elegantly composed, handily composed papers. In all probability, the altering group of your school that gets alloted the exposition of the week won't have indistinguishable expertise and composing capacities from you do. Thusly, your exposition doesn't get composed through your typical comp osing skills.To start with, essayists invest loads of time and vitality on the thoughts that make up the subject, so as to make them so they are composed well. They arrange the blueprint of the article to be as it will end. As they take a shot at making it right, they change the content and the whole structure and they alter it similarly as the article should be altered. To make it, they don't change the first thought by any stretch of the imagination, however they would alter it so the point isn't over-shuffled.Writers invest more energy thinking about the subject and the topic that they ought to build up the theme. The theory that they would put as the central matter of the paper gets changed into the article so as to make it as the paper is appropriately composed. They reconsider and rename it on numerous events. This gives them an opportunity to think about the blemishes of the first content.&l t;p>In the creative cycle, the record gets marked of by editors who will examine and detect the blunders in the piece. For the most part, the mistakes will be the ones that can't be seen from the outset. The troublesome activity that these editors will do isn't on the quantity of mix-ups in the record. No, its hardest piece is recognizing the slip-ups in the archives. It will give the editors the difficult time that might be for another round of editing.For scholars, the term of how to compose a six-page school paper tests isn't difficult to comprehend. The activity of an article essayist is to make it with the goal that the sentiment that they are telling is totally framed and elegantly composed. In spite of the fact that it isn't generally along these lines, yet they don't really need to know the word reference of the English language. Rather, they will invest a ton of energy in finding the specific use of the words and e xpressions that they will use in the article.It can likewise assist you with getting familiar with legitimate utilization of the words and the general method of writing so as to make the point spotless and clear. Along these lines, the author can make it increasingly imaginative and intriguing and help their perusers to comprehend what the writer implied when the individual in question composed the article. In this way, the creative cycle of how to compose a six-page school paper tests is anything but difficult to get started.

Friday, May 29, 2020

Vlsi design and embedded systems - Free Essay Example

CHAPTER 1 INTRODUCTION 1.1 Motivation Phase locked loop (PLL) [1-3] is the heart of the many modern electronics as well as communication system. Recently plenty of the researches have conducted on the design of phase locked loop (PLL) circuit and still research is going on this topic. Most of the researches have conducted to realize a higher lock range PLL with lesser lock time [4] and have tolerable phase noise. The most versatile application of the phase locked loops (PLL) is for clock generation and clock recovery in microprocessor, networking, communication systems, and frequency synthesizers. Phase locked-loops (PLLs) are commonly used to generate well-timed on-chip clocks in high-performance digital systems. Modern wireless communication systems employ Phase Locked Loop (PLL) mainly for synchronization, clock synthesis, skew and jitter reduction [5]. Phase locked loops find wide application in several modern applications mostly in advance communication and instrumentation systems. PLL being a mixed signal circuit involves design challenge at high frequency. Since its inspection in early 1930s, where it was used in the synchronization of the horizontal and vertical scans of television, it has come to an advanced form of integrated circuit (IC). Today found uses in many other applications. The first PLL ICs were available around 1965; it was built using purely analog component. Recent advances in integrated circuit design techniques have led to the development of high performance PLL which has become more economical and reliable. Now a whole PLL circuit can be integrated as a part of a larger circuit on a single chip. There are mainly five blocks in a PLL. These are phase frequency detector (PFD), charge pump (CP), low pass loop filter (LPF), voltage controlled oscillator (VCO) and frequency divider. Presently almost all communication and electronics devices operate at a higher frequency, so for that purpose we need a faster locking PLL. So there are a lot of challenges in designing the mentioned different blocks of the PLL to operate at a higher frequency. And these challenges motivated me towards this research topic. In this work mainly the faster locking of the PLL is concentrated by properly choosing the circuit architectures and parameters. The optimization of the VCO circuit is also carried out in this work to get a better frequency precision. 1.2 Organization of Thesis Before going into the details of the PLL, the motivation behind this work is mentioned in the Chapter 1 of the thesis. Chapter 2 briefly describes the whole PLL system. An introduction to the PLL circuit is mentioned in the section 2.1. Section 2.2 contains the detail architecture of the whole PLL system. Different types of PLLs are mentioned in the section 2.3. Section 2.4 explains the basic terms used in the PLL system while the consecutive sections give the details about the noise and application of the PLL. Chapter 3 builds the concepts of optimization. Definition of optimization technique and different circuit optimization techniques are presented in section 3.1 and 3.2 respectively. Section 3.3 gives the brief outline of the concept of geometric programming and convex optimization. The optimization of the CSVCO circuit is explained in section 3.4. The design and synthesis of the PLL is described in Chapter 4. The different design environments used in this work is mentioned in the section 4.1. The adopted design procedure is explained in section 4.2. Section 4.3 gives the design specifications and parameters of the work. The simulation results of the different circuits used in the PLL are depicted in the different sections of the Chapter 5. The performance of the CSVCO designed using convex optimization is compared with that of the traditional method in section 5.3. Section 5.5 gives the different simulation results of the PLL and its performance comparison between schematic and post layout level. At last Chapter 6 provides the conclusion that inferred from the work. CHAPTER 2 PHASE LOCKED LOOP 2.1 Introduction A PLL is a closed-loop feedback system that sets fixed phase relationship between its output clock phase and the phase of a reference clock. A PLL is capable of tracking the phase changes that falls in this bandwidth of the PLL. A PLL also multiplies a low-frequency reference clock CKref to produce a high-frequency clock CKout this is known as clock synthesis. A PLL has a negative feedback control system circuit. The main objective of a PLL is to generate a signal in which the phase is the same as the phase of a reference signal. This is achieved after many iterations of comparison of the reference and feedback signals. In this lock mode the phase of the reference and feedback signal is zero. After this, the PLL continues to compare the two signals but since they are in lock mode, the PLL output is constant. The basic block diagram of the PLL is shown in the Figure 2.1. In general a PLL consists of five main blocks: Phase Detector or Phase Frequency Detector (PD or PFD) Charge Pump (CP) Low Pass Filter (LPF) Voltage Controlled Oscillator (VCO) Divide by N Counter The Phase frequency Detector (PFD) is one of the main parts in PLL circuits. It compares the phase and frequency difference between the reference clock and the feedback clock. Depending upon the phase and frequency deviation, it generates two output signals UP and DOWN. The Charge Pump (CP) circuit is used in the PLL to combine both the outputs of the PFD and give a single output. The output of the CP circuit is fed to a Low Pass Filter (LPF) to generate a DC control voltage. The phase and frequency of the Voltage Controlled Oscillator (VCO) output depends on the generated DC control voltage. If the PFD generates an UP signal, the error voltage at the output of LPF increases which in turn increase the VCO output signal frequency. On the contrary, if a DOWN signal is generated, the VCO output signal frequency decreases. The output of the VCO is then fed back to the PFD in order to recalculate the phase difference, and then we can create closed loop frequency control system. 2.2 PLL Architecture The architecture of a charge-pump PLL is shown in Figure 2.2. A PLL comprises of several components. They are (1) phase or phase frequency detector, (2) charge pump, (3) loop filter, (4) voltage-controlled oscillator, and (5) frequency divider. The functioning of each block is briefly explained below. 2.2.1 PhaseFrequency Detector The Phase frequency Detector (PFD) is one of the main part in PLL circuits. It compares the phase and frequency difference between the reference clock and the feedback clock. Depending upon the phase and frequency deviation, it generates two output signals UP and DOWN. Figure 2.3 shows a traditional PFD circuit. If there is a phase difference between the two signals, it will generate UP or DOWN synchronized signals. When the reference clock rising edge leads the feedback input clock rising edge UP signal goes high while keeping DOWN signal low. On the other hand if the feedback input clock rising edge leads the reference clock rising edge DOWN signal goes high and UP signal goes low. Fast phase and frequency acquisition PFDs [6-7] are generally preferred over traditional PFD. 2.2.2ChargePump and Loop Filter Charge pump circuit is an important block of the whole PLL system. It converts the phase or frequency difference information into a voltage, used to tune the VCO. Charge pump circuit is used to combine both the outputs of the PFD and give a single output which is fed to the input of the filter. Charge pump circuit gives a constant current of value IPDI which should be insensitive to the supply voltage variation [8]. The amplitude of the current always remains same but the polarity changes which depend on the value of the UP and DOWN signal. The schematic diagram of the charge pump circuit with loop filter is shown in the Figure 2.4. When the UP signal goes high M2 transistor turns ON while M1 is OFF and the output current is IPDI with a positive polarity. When the down signal becomes high M1 transistor turns ON while M2 is OFF and the output current is IPDI with a negative polarity. The charge pump output current [3] is given by IPDI=IPUMPIPUMP4 =2IPUMP4 =IPUMP2 =KPDI (1) Where KPDI=IPUMP2 (amps/radian) (2) The passive low pass loop filter is used to convert back the charge pump current into the voltage. The filter should be as compact as possible [9].The output voltage of the loop filter controls the oscillation frequency of the VCO. The loop filter voltage will increase if Fref rising edge leads Fin rising edge and will decrease if Fin rising edge leads Fref rising edge. If the PLL is in locked state it maintains a constant value. The VCO input voltage is given by Vinvco = KF IPDI (3) Where KF is the gain of the loop filter. 2.2.3Voltage ControlledOscillator An oscillator is an autonomous system which generates a periodic output without any input. The most popular type of the VCO circuit is the current starved voltage controlled oscillator (CSVCO). Here the number of inverter stages is fixed with 5. The simplified view of a single stage current starved oscillator is shown in the Figure 2.5. Transistors M2 and M3 operate as an inverter while M1 and M4 operate as current sources. The current sources, Ml and M4, limit the current available to the inverter, M2 and M3; in other words, the inverter is starved for current. The desired center frequency of the designed circuit is 1GHz with a supply of 1.8V. The CSVCO is designed both in usual manner as mentioned in [3], [10, 11]. The general circuit diagram of the current starved voltage controlled oscillator is shown in the Figure 2.6. To determine the design equations for the CSVCO, consider the simplified view of VCO in Figure 2.5. The total capacitance on the drains of M2 and M3 is given by Ctot=52Cox(LpWp+LnWn) (4) The time it takes to charge Ctot from zero to VSP with the constant current ID4 is given by t1=VSPID4Ctot (5) While the time it takes to discharge Ctot from VDD to VSP is given by t1=VDD-VSPID1Ctot (6) If we set ID4= ID1=ID then the sum of t1 and t2 is given by t1+t2=VDDIDCtot (7) The oscillation frequency of CSVCO for N number of stage is fosc=1Nt1+t2=IDNCtotVDD (8) This is equal to fcenter when Vinvco=VDD2 (9) The gain of the VCO is given by KVCO=fmax-fminVmax-Vmin HzV (10) 2.2.4 FrequencyDivider The output of the VCO is fed back to the input of PFD through the frequency divider circuit. The frequency divider in the PLL circuit forms a closed loop. It scales down the frequency of the VCO output signal. A simple D flip flop (DFF) acts as a frequency divider circuit. The schematic of a simple DFF based divide by 2 frequency divider circuit is shown in the Figure 2.7. 2.3 Types of PLL There are mainly 4 types of PLL are available. They are . Liner PLL Digital PLL All Digital PLL Soft PLL 2.4 Terms in PLL 2.4.1 Lock in Range Once the PLL is in lock state what is the range of frequencies for which it can keep itself locked is called as lock in range. This is also called as tracking range or holding range. 2.4.2 Capture Range When the PLL is initially not in lock, what frequency range can make PLL lock is called as capture range. This is also known as acquisition range. This is directly proportional to the LPF bandwidth. Reduction in the loop filter bandwidth thus improves the rejection of the out of band signals, but at the same time the capture range decreases, pull in time becomes larger and phase margin becomes poor. 2.4.3 Pull in Time The total time taken by the PLL to capture the signal (or to establish the lock) is called as Pull in Time of PLL. It is also called as Acquisition Time of PLL. 2.4.4 Bandwidth of PLL Bandwidth is the frequency at which the PLL begins to lose the lock with reference. 2.5 Noises in PLL The output of the practical system deviates from the desired response. This is because of the imperfections and noises in the system. The supply noise also affects the output noise of the PLL system [12]. There are mainly 4 types of noises. They are explained below. 2.5.1 Phase Noise The phase fluctuation due to the random frequency variation of a signal is called as phase noise. This is mostly affected by oscillators frequency stability. The main sources of the phase noise in PLL are oscillator noise [12-15], PFD and frequency divider circuit. The main components of the phase noise are thermal and flicker noise. 2.5.2 Jitter A jitter is the short term-term variations of a signal with respect to its ideal position in time [16-19]. This problem negatively impacts the data transmission quality. Jitter and phase noise are closely related and can be computed one from another [18]. Deviation from the ideal position can occur on either leading edge or trailing edge of signal. Jitter may be induced and coupled onto a clock signal from several different sources and is not uniform over all frequencies. Excessive jitter can increase bit error rate (BER) of communication signal [19]. In digital system Jitter leads to violation in time margins, causing circuits to behave improperly. 2.5.3 Spur Non-desired frequency content not related to the frequency of oscillation and its harmonics is called as Spur. There are mainly two types of spur. They are reference spur and fractional spur. Reference spur comes into picture in an integer PLL while fractional spur plays a major role in fractional PLL. When the PLL is in lock state the phase and frequency inputs to the PFD are essentially equal. There should not be any error output from the PFD. Since this can create problem, so the PFD is designed such that, in the locked state the current pulses from the CP will have a very narrow width as shown in the Figure 2.9. Because of this the input control voltage of the VCO is modulated by the reference signal and thus produces Reference Spur [20]. 2.5.4 Charge Pump Leakage Current When the CP output from the synthesizer is programmed to the high impedance state, in practice there should not be any current flow. But in practical some leakage current flows in the circuit and this is known as charge pump leakage current [20]. 2.6 Applications of PLL The demand of the PLL circuit increases day by day because of its wide application in the area of electronics, communication and instrumentation. The recent applications of the PLL circuits are in memories, microprocessors, hard disk drive electronics, RF and wireless transceivers, clock recovery circuits on microcontroller boards and optical fiber receivers. Some of the PLL applications are mentioned below. 1.FrequencySynthesis A frequency synthesizer is an electronic system for generating a range of frequencies from a single fixed time base or oscillator. 2.Clock Generation Many electronic systems include processors of various sorts that operate at hundreds of megahertz. Typically, the clocks supplied to these processors come from clock generator PLLs, which multiply a lower-frequency reference clock (usually 50 or 100 MHz) up to the operating frequency of the processor. The multiplication factor can be quite large in cases where the operating frequency is multiple GHz and the reference crystal is just tens or hundreds of megahertz. 3.Carrier Recovery (Clock Recovery) Some data streams, especially high-speed serial data streams (such as the raw stream of data from the magnetic head of a disk drive), are sent without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a PLL. This process is referred to as clock recovery. 4. SkewReduction This is one of the very popular and earliest uses of PLL. Suppose synchronous pair of data and clock lines enter a large digital chip. Since clock typically drives a large number of transistors and logic interconnects, it is first applied to large buffer. Thus, the clock distributed on chip may suffer from substantial skew with respect to data. This is an undesirable effect which reduces the timing budget for on-chip operations. 5. Jitterand Noise Reduction One desirable property of all PLLs is that the reference and feedback clock edges be brought into very close alignment. The average difference in time between the phases of the two signals when the PLL has achieved lock is called the static phase offset. The variance between these phases is called tracking jitter. Ideally, the static phase offset should be zero, and the tracking jitter should be as low as possible. CHAPTER 3 CONVEX OPTIMIZATION OF VCO IN PLL 3.1 What is an optimization technique? Optimization technique is nothing but the finding of the action that optimizes i.e. minimizes or maximizes the result of the objective function. Optimization technique is applied to the circuits aiming at finding out the optimized circuit design parameter to achieve either the best performance or the desired performance. Optimization techniques are a set of most powerful tools that are used in efficiently handling the design resources and there by achieve the best result. Mainly optimization techniques are applied to the circuit for the selection of the component values, devices sizes, and value of the voltage or current source. 3.2 Types of circuit optimization method There are mainly four types of circuit optimization methods exist. They are Classical optimization Knowledge based optimization Global optimization method Convex optimization and geometric programming 3.2.1 Classical Optimization Methods: In case of analog circuit CAD, classical optimization methods [21], such as steepest descent, sequential quadratic programming, and Lagrange multiplier methods are mainly used. These methods are used with more complicated circuit models, including even full SPICE simulations in each iteration. This method can handle a wide variety of problem. For this there is a need of a set of performance measures and computation of one or more derivatives. The main disadvantage of the classical optimization methods is that the global optimal solution is not possible. This method fails to find a feasible design even one exist. This method gives only the local minima instead of global solution. Since many different initial designs are considered to get the global optimization, the method becomes slower. Because of the human intervention (to give good initial designs), the method becomes less automated. The classical methods become slow if complex models are used. 3.2.2 Knowledge-Based Methods: Knowledge-based and expert-systems methods such as genetic algorithm or evolution systems, systems based on Fuzzy logic, and heuristics-based systems have also been widely used in analog circuit CAD [21]. In case of knowledge based methods, there are few limitations on the types of problems, specifications, and performance measures that are to be considered. These methods do not require the computation of the derivatives. This is not possible to find a global optimal design solution using these methods. The final design is decided on the basis of the initial design chosen and the algorithm parameters. The disadvantage of the knowledge based methods is that they simply fail to find a feasible solution even when one may exist. There is a need of human intervention during the design and the training process. 3.2.3 Global Optimization Methods: Global optimization methods such as branch and bound and simulated annealing are also used in analog circuit design [21]. These methods are guaranteed to find the global optimal design solution. The global optimal design is determined by the branch and bound methods unambiguously. In each iteration, a suboptimal feasible design and also a lower bound on the achievable performance is maintained by this method. This enables the algorithm to terminate non-heuristically, i.e., with complete confidence that the global design has been found within a given tolerance. The branch and bound method is extremely slow, with computation growing exponentially with problem size. The trapping in a locally optimal design can be avoided by using simulated annealing (SA). This method can compute the global optimal solution but not guaranteed. Since there is no real-time lower bound is available, so termination is heuristic. This method can also handle a wide variety of performance indices and objects. T he main advantage of SA is that it handles the continuous variables and discrete variables problems efficiently and reduces the chances of getting a non-globally optimal design. The only problem with this method is that it is very slow and can not guarantee a global optimal solution. 3.2.4 Convex Optimization and Geometric Programming Methods: Geometric programming methods are special optimization problems in which the objective and constraint functions are all convex [22-24]. Convex optimization technique can solve the problems having a large number of variables and constraints very efficiently [22]. The main advantage of this method for which people generally adopt is that the method gives the global solution. Infeasibility is unambiguously detected. Since a lower bound on the achievable performance is given, so the method uses a completely non- heuristic stopping criterion. 3.3 Geometric programming and convex optimization Geometric programming is a special type of optimization technique in which all the objective must be convex. Before applying this technique it has to confirm that whether the given problem is convex optimization problem or not. Convex optimization problem means the problem of minimizing a convex function subject to convex inequality constraints and linear equality constraints. In IC integration convex optimization and geometric programming has become a more efficient computational tool for optimization purpose. This method has an ability to handle thousands of variables and constraints and solve efficiently. The main advantage of convex optimization technique is that it gives the global optimized value and the robust design. The fact that geometric programs can be solved very efficiently has a number of practical consequences. For example, the method can be used to simultaneously optimize the design of a large number of circuits in a single large mixed-mode integrated circuit. The de signs of the individual circuits are coupled by constraints on total power and area, and by various parameters that affect the circuit coupling such as input capacitance, output resistance, etc. Convex optimization is used to find out the optimized value of these parameter and sizing of the devices in the circuit [25]. Another application is to use the efficiency to obtain robust designs i.e., designs that are guaranteed to meet a set of specifications over a variety of processes or technology parameter values. This is done by simply replicating the specifications with a (possibly large) number of representative process parameters, which is practical only because geometric programs with thousands of constraints are readily solved. A real valued function fx defined on an interval (space) is called convex if ftx1+1-tx2tfx1+1-tfx2 (11) For every t,0t1 and x1x2 In the Figure 3.1 function fx is represented as a convex function on an interval. The convex optimization problem is in the form of minimize f0x Subjected to fix1 , i=1, 2, 3, m gix=1 , i=1, 2, 3, p xi1 , i=1, 2, 3, n Where fix is a posynomial function gix is a monomial function Let x1,x2xn be n real positive variables. We can denote the vector (xi,xi.xi) of these variables asx. A function f is called a posynomial function of x if it has the form fix1,x2xn=k=1tCkx11kx22k..xnnk (12) Where Cj0 and ij R. The coefficients Cj must be nonnegative but the exponents ij can be any real numbers including negative or fractional. When there is exactly one nonzero term in the sum i.e. t=1 and C10, we call f is a monomial function. 3.3.1 Advantages: Handle thousands of variables and constraints and solve efficiently. Global optimization can be obtained. 3.3.2 Disadvantages: * Strictly limited to types of problems, performance specification and objectives that can be handled. 3.4 Optimization of the VCO circuit In my earlier design of the VCO circuit, the sizes of all the five inverter stages are same. Now the convex optimization technique is applied to find out the optimal scaling ratio of the different inverter stages to get the optimal design with a better performance. There are 5 inverter stages and the design has to give a delay of 100ps. The load capacitance of the VCO circuit is 65 fF. All these design constraints are formulated and applied to the convex optimization technique. Mainly optimization techniques are applied for selection of component values and transistor sizing. In this work I have used the geometric programming technique to find out the optimized scaling ratio of the different stages in CSVCO to meet the desired center frequency with lesser deviation. Let xi is the scaling ration of the ith stage, CL is the load capacitance, and D is the total delay of the inverter stages then optimization problem is in the form of Minimize sum (xi) Subjected to CLCLmax DDmax Where CLmax and Dmax are required design parameters and has a constant value. CHAPTER 4 DESIGN AND SYNTHESIS OF PLL 4.1 Design Environment The schematic level design entry of the circuits is carried out in the CADENCE Virtuoso Analog Design Environment. The layout of the PLL is designed in Virtuoso XL using GPDK090 library. In order to analyze the performances, these circuits are simulated in the Spectre simulator of CADENCE tool. Different performance indices such as phase noise, power consumption and lock time are measured in this environment. Transient, parametric sweep and phase noise analyses are carried out in this work to find out the performances of the circuit. The optimization of the current starved VCO circuit, the scale factor for transistor sizing is found out using the MATLAB environment. 4.2 Design Procedure 4.2.1 VCO Design Since VCO is the heart of the whole PLL system, it should be designed in a proper manner. The design steps for the current starved VCO are as follows. Step 1 Find the value of the propagation delay for each stage of the inverter in the VCO circuit using the following equation. p=1Nf (13) Where p= phl= plh= half of the propagation delay time of the inverter N= no of inverter stages f= required center frequency of oscillation Step 2 Find the WL ratio for the transistors in the different inverter stages using the equation in below. WL n=CloadphlnCoxVdd-VT,n2VT,nVdd-VT,n+ln4Vdd-VT,nVdd-1 (14) WL p=CloadplhpCoxVdd-VT,p2VT,pVdd-VT,p+ln4Vdd-VT,pVdd-1 (15) Step 3 After finding the WL ratio, find the values for W and L. Step 4 Find the value of the total capacitance form the expression Ctot=52Cox(LpWp+LnWn) (16) Where Cox is the oxide capacitance Lp,Wp,Ln,Wn is the width and length of the PMOS and NMOS transistors in the inverter stages. Step 5 Calculate the value of drain current for the center frequency which is given by IDcenter=NCtotVddf (17) Step 6 Find the WL ratio for the current starving transistors in the circuit from the drain current expression which is represented as WL n=2IDcenternCoxVgs-VT,n2 (18) Similarly WL p=2.5WL n (19) 4.2.2 Design of Phase Locked Loop The value of the charge pump current and the component parameters of the loop filter play a major role in the design of the phase locked loop circuit. The value of the lock time mainly depends upon these parameters. So while designing the circuit proper care should be taken in calculating these parameters. For the given values of reference(Fref) and output frequency(Fout) as well as the lock in range, the following steps to be carried out in designing the filter circuit. Step 1 Find the value of the divider circuit to be used which is given by n=FoutFref (20) Step 2 Find the value of the natural frequency (n) from the lock in range as given below lock in range=2n (21) Step 3 Find the value of the charge pump gain (KPDI) from the charge pump current used in the circuit which is given by KPDI=Ipump2 (Amps/radian) (22) Step 4 Find the value of the gain of the VCO (Kvco) circuit from the characteristics curve using the following expression. Kvco=fmax-fminVmax-Vmin (Hz/V) (23) Step 5 Find the values of the loop filter component parameters using the following expressions. C1=KPDIKvcoNn2 (24) C2=C110 (25) R=2nC1 (26) 4.3 Design Specifications and Parameters 4.3.1 VCO Design Specification The current starved VCO design specifications are mentioned in the following table. Parameter Value Center frequency 1GHz No. of inverter stage 5 Inverter delay 100ps Load capacitance 65fF Supply voltage 1.8V Table 1 VCO design specifications 4.3.2 VCO Design Parameters Parameter Value Width of Current starved PMOS(WPCS) 2.33m Width of Current Starved NMOS(WnCS) 140nm Width of PMOS in Inverter(WP) 2.44m Width of NMOS in Inverter(Wn) 150nm LPCS = LnCS = LP = Ln = L 100nm Table 2 List of design parameters of the CSVCO circuit 4.3.3 PLL Design Parameters The whole PLL system design specifications and parameters are shown in the Table 3. Parameter Value Reference frequency((Fref) 500 MHz output frequency(Fout) 1 GHz Lock in range 100 MHz Supply voltage 1.8 V Divider circuit By 2 Charge pump current(Ipump) 600 A Capacitor (C1) 15 pF Capacitor (C2) 1.5 pF Resistor (R) 1.384 K Table 3 PLL design specifications and parameters CHAPTER 5 SIMULATION RESULT AND DISCUSSION 5.1 Phase Frequency Detector The Pass Transistor DFF PFD circuit is shown in Figure 5.1. The PFD is same as to a dynamic two-phase master-slave pass-transistor flip-flop. The clock skew is minimized by using single edge clocks. In this design synchronous reset is used for master while asynchronous reset is used for slave. i.e., the reset is allowed only when the slave latch is transparent. The operating range of the design is increased with the help of synchronous resetting and also the power consumption is reduced compared to the traditional PFD. If the master latch is reset while it is transparent, then there will be significant short-circuit current will produce, resulting in more power. The output of the PFD when Fref signal rising edge leads Fin signal rising edge and vice versa is shown in the Figure 5.2 and Figure 5.3 respectively. 5.2 Charge Pump and Loop Filter When the reference signal clock edge leads the feedback clock edge, the UP signal of the PFD goes high. So to make both the clock have rising edge at the same time the VCO output signal frequency has to be increased. For this purpose an increase in control voltage is needed from the output of charge pump and loop filter circuit. The simulation result which is shown in the Figure 5.4 below gives an increase in the control voltage at the output of the loop filter circuit. From the Figure 5.4 its clear that the control voltage increases for a period during which the UP signal of the PFD remains high. In the other case a decrease in the control voltage is produced at the output of the filter circuit which is shown in the Figure 5.5. When the rising of feedback signal leads the reference signal rising edge the control voltage decreases for the period during which the DOWN signal of the PFD remains high. 5.3 Voltage Controlled Oscillator 5.3.1 Result using traditional method The heart of the PLL circuit is the voltage controlled oscillator. The circuit is designed to give a center frequency of oscillation of 1 GHz. The frequency of oscillation of the output signal for the different input control voltage is mentioned in the Table 4. The center frequency of oscillation at an input control voltage of VDD/2 is 1.012 GHz. The output signal of the VCO at a control voltage of VDD/2 is shown in the Figure 5.6. Control Voltage (VC)(in volt) Frequency of Oscillation (f) (in MHz) 0.103 24.415 0.154 50.929 0.206 91.05 0.257 139.32 0.309 188.179 0.36 234.277 0.411 282.125 0.463 342.256 0.514 412.889 0.566 489.48 0.617 569.178 0.669 650.037 0.720 731.72 0.771 812.946 0.823 893.63 0.874 973.461 Control Voltage Frequency of Oscillation 0.926 1051.851 0.977 1128.02 1.03 1200.67 1.08 1271.818 1.13 1338.398 1.18 1401.32 1.23 1460.798 1.29 1517.121 1.34 1570.371 1.39 1620.798 1.44 1668.416 1.49 1713.913 1.54 1757.073 1.59 1798.081 1.65 1836.986 1.7 1873.865 1.75 1909.109 1.8 1943.021 Table 4 Oscillating frequency of the VCO output signal for different control voltage The VCO characteristics curve is shown in the Figure 5.7. The X-axis of the curve represents the input control voltage while the Y-axis represents the corresponding frequency of oscillation. The gain of the CSVCO circuit is 1.531 GHz/V. The phase noise of the VCO in the schematic level is found to be -82.87 dBc/Hz. The phase noise plot for schematic level is shown in the Figure 5.8. The layout of the 5 stage current starved VCO is shown in the Figure 5.9. The schematic and post layout level simulation results are compared in the Table 5. Parameter Schematic Result Post-Layout Result Frequency(f) 1.012 GHz 1.00256 GHz Frequency Deviation(f) 12 MHz 2.56 MHz Power(P) 432.456 W 480.63 W Phase Noise @1MHz offset -82.7 dBc/Hz -84.88 dBc/Hz Table 5 Comparison of schematic and post layout level simulation results 5.3.2 Result using convex optimization method Using convex optimization method the scaling ratio is found out to satisfy the center frequency of oscillation (i.e. delay of the circuit) from the MATLAB environment. The scaling ratio for different stages of the inverter in the VCO is 1,1,1,1 and 1.4058. The scaling ratio result is shown in the Figure 5.10. Now the transistor sizes are modified according to the scaling ratio. Since the scaling factor of all the stages are 1 except 5th stage, so the transistor sizing of the 5th stage has only changed to get the better frequency precision. The sizes of the transistors of CSVCO optimized using convex optimization technique are listed out in the Table 6. Before optimization the centre frequency of the oscillation is found out 1.012GHz. And after applying the convex optimization and geometric programming to this circuit, the centre frequency of oscillation is 1000.0457MHz. So the frequency deviation from its centre frequency is reduced to .00457% from 1.2%. The performance of CSVCO for both traditional and geometric programming is compared in the Table 7. The comparison of control voltage versus oscillating frequency characteristics of the CSVCO circuit is shown in the Figure 5.11. Stage Parameter value 1 WPCS WnCS WP Wn 2.33m 140nm 2.44m 150nm 2 WPCS WnCS WP Wn 2.33m 140nm 2.44m 150nm 3 WPCS WnCS WP Wn 2.33m 140nm 2.44m 150nm 4 WPCS WnCS WP Wn 2.33m 140nm 2.44m 150nm 5 WPCS WnCS WP Wn 3.28m 195nm 3.435m 215nm Table 6 Size of the transistors of CSVCO circuit after optimization Factor CSVCO using traditional method CSVCO using convex optimization method Frequency(f) 1.012GHz 1.0000457GHz Frequency Deviation(f) 12MHz 45.7KHz Power(P) 432.456W 539.65W Phase Noise @1MHz offset -82.7 dBc/Hz -82.6 dBc/Hz KVCO 1.531GHz/V 1.5926GHz/V Table 7 Performance comparison of CSVCO designed using traditional method and convex optimization 5.4 Frequency Divider The circuit diagram of a pass transistor based DFF frequency divider circuit is shown in the Figure 5.12. The circuit divides the frequency by a factor of 2. The simulation result of the divide by 2 circuits is shown in the Figure 5.13 5.5 Phase Locked Loop The output of the charge pump and loop filter circuit i.e. the control voltage will maintain a constant value when the references signal and feedback signal are in lock. The control voltage of PLL for the schematic level is shown in the Figure 5.14. From the Figure 5.14 its clear that the control maintains the constant value of 0.9 V at time 280.6 ns. So the lock time of PLL is 280.6 ns. The layout of the PLL is shown in the Figure 5.15. The most of the area of the PLL is consumed by the resistor and capacitor used in the filter network. Different signals like UP, DOWN, Control Voltage, reference signal and feedback input signal of the PLL in the lock state are shown in the Figure 5.16 and Figure 5.17 for schematic level and post layout level respectively. From the Figure 5.16 and 5.17 its clear that when the control voltage is constant, the reference signal and the feedback input signal are almost similar as their phase and frequency are approximately same. The phase noise analysis of the PLL is carried out both in the schematic as well as in the post layout level. The phase noise is found to be -86.21 dBc/Hz and -101.7 dBc/Hz in schematic and post layout level respectively. The phase noise variation of the PLL both in schematic and post layout level simulation are shown in the Figure 5.18 and 5.19 respectively. The performance comparison of the PLL both in schematic and post layout level simulation are mentioned in the Table 8. Parameter Result of Schematic Level Simulation Result of Post Layout Level Simulation Technology 90 nm 90 nm VDD 1.8 V 1.8 V Lock Time 280.6 ns 345.5 ns Frequency 1 GHz 1 GHz Maximum Power Consumption 11.9 mW 10.408 mW Phase Noise @ 1MHz offset -86.21 dBc/Hz -101.7 dBc/Hz Table 8 Performance comparison of PLL circuit CHAPTER 6 CONCLUSION AND FUTURE WORK In this work a PLL with a better lock time is presented. The lock time of the PLL is found to be 280.6 ns. The PLL circuit consumes a power of 11.9 mW from a 1.8 V D.C. supply The lock time of the PLL mainly depends upon the type of PFD architecture used and the parameters of the charge pump and loop filter. So by properly choosing the PFD architecture and adjusting the charge pump current and the loop filter component values a better lock time can be achieved. The centre frequency of oscillation of the VCO depends upon the sizing of the transistors. The frequency deviation from the desired value can be reduced by properly choosing the transistor sizes. By applying the convex optimization technique with frequency of oscillation as the main objective function, the deviation of oscillation frequency is minimized to 0.00457% from 1.2%. Here the convex technique to find out the transistor sizing to meet only the desired frequency specification. The other constraints like area, power and phase noise can also be applied.

Tuesday, May 26, 2020

Writing an Accomplished Nursing Entrance Essay Sample

Writing an Accomplished Nursing Entrance Essay SampleFor those aspiring to become a registered nurse, you should know that entering the world of nursing is not the easy job. There are many factors and pitfalls that a nursing student needs to overcome in order to become a successful and competent nurse. One of these factors is the selection of impressive nursing entrance essay samples. When you find one that you can admire, you will be able to determine if you are capable of giving a convincing yet appealing answer when it comes to this type of essay exam.The Nursing Entrance Essay sample test is given by different training schools for students who are considering the nursing career. It is the first thing a student must do to make a decision if he or she wants to continue with the nursing profession. If you are the kind of person who loves to explore a subject and finding ways to explain it better, then the Entrance Essay would be something you can really enjoy. Many people who have b een studying this test and solving this problem have found a way to answer their doubts. It gives the students an opportunity to get inside the minds of their examiners so that they can see what they are doing and they can give an effective answer.The real test for all of us is to come up with an interesting application or conclusion to give our answer. The information you write here is what will decide whether you pass or fail this test. If you fail this test, you will have to take more tests that will actually matter in determining whether you are qualified to become a nurse. If you fail your Entrance Essay test, there is a strong possibility that you will not be able to continue with the curriculum and will have to take the Entrance Essay test again.Because of this, you must always prepare yourself for the Entrance Essay test. You will find several sources on the Internet where you can get valuable information on how to write an impressive nursing entrance essay. They contain a l ist of ideas that you need to keep in mind so that you will not lose your mind. This may sound a bit obvious but it is true.An example of a well-written Nursing Entrance Essay sample is when you are given two possible answers and asked to choose which of them is the most convincing one. However, you do not have to be asked to choose just because it is asked. To give a good answer, you need to analyze the problem and then choose the best answer that will help you solve the problem and which will also give an overall answer that you can appreciate.The Entrance Essay is given twice a year, once before and after the New Student Orientation Program. There are other times when it will be given as well. If you are assigned to do it during orientation, then you have to make sure that you have all the necessary material to give a convincing answer to your examiners. Because the Entrance Essay exam is usually given before and after the Orientation, this makes it necessary for you to have a li st of answers prepared to give when it is your turn to answer.Do not panic if you have no idea on how to write an impressive Nursing Entrance Essay sample. In fact, there are several ways to give an answer that is perfect for an Entrance Essay exam. You can use words that are associated with nursing, write about your passion or your personal experiences and use examples that you have encountered in your daily life.Since there are several ways on how to write an impressive Nursing Entrance Essay sample, you should use a combination of all these tools in order to give the best answer possible. A well-written Nursing Entrance Essay sample may seem simple but there are some students who tend to make mistakes because they do not have all the details and facts in mind. These mistakes are usually discovered by the examiners when they read the answers because of the absence of these details.

Sunday, May 24, 2020

Writers Online at a Glance

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Thursday, May 21, 2020

Sample Essay About Video Games

<h1>Sample Essay About Video Games</h1>If you are taking a shot at getting an Associate's degree in Educational Technology, at that point an example article about computer games would be an incredible method to assist. On the off chance that you have ever played a round or the like, at that point you most likely do as such at any rate on more than one occasion per week. Regardless of whether it is the conventional dashing, shooting, battling or investigating, you have likely partaken in one of these games on a standard basis.What are the manners by which you can utilize an example article to help you with regards to expounding on computer games? There are a wide range of points of view, and various topics that can be utilized to portray the different parts of these games. A decent example can give you the spine for expounding on the various components that the gamer may view.Gaining a mor e extensive information on the gaming and gamer subculture is a significant activity. This will assist you with expounding on your gaming encounters in a progressively positive light. You can clarify how playing these games truly causes you to feel, and the delights that you involvement in the information that you are helping other people to master something through your activities. This can assist you with describing the game and the gamer culture from an alternate point of view, permitting you to depict the gaming network from a third individual viewpoint, rather than simply taking a gander at them from the perspective of the player.Another angle that you will need to consider is the means by which the games are played in a social viewpoint. These games are frequently played as a type of amusement, as opposed to achieve anything in a serious perspective. This implies you ought to consider depicting in a positive manner the kinships that are ma de by the gaming condition. Recall that numerous gamers have an exceptional relationship with their companions, family and different gamers. This can assist you with making an increasingly positive depiction of gaming with the extra commitment of these friends.Describing the excitement of having beaten a difficult level is another energizing angle that can be utilized to portray the encounters of a gamer. At the point when somebody has beaten a degree of a specific game, they are said to have beaten the level. These levels are viewed as exceptionally hard to beat, and regularly set aside a long effort to beat. The component of rivalry is the thing that assists with making these difficult levels, and this can be delineated in a couple of various ways.Those who have beaten these hard levels will frequently help each other through their own difficulties. This can incorporate offering guidance, and sharing tips on the most proficient method to finish a test. For instance, if a game has different levels, and a gamer is experiencing difficulty with a specific level, they may offer assistance to that gamer to attempt to finish the level for them.Playing these games is probably the most ideal approaches to collaborate with others from a genuine perspective. Expounding on the parts of gaming is one approach to allow yourself to develop these encounters, and the advantages that you can pick up from it.